Alam Romo
Currently Working towards my master's degree at Cal Poly. Interested in VLSI, AI, and the intersection of both. Master's project focuses on investigating tradeoffs between accuracy, latency, and resource consumption in FPGA-based AI accelerators created using hls4ml.
I have completed the requirements for a bachelor's degree at Cal Poly in Electrical Engineering as well. My senior project was the ground-up design of a automated bike lock with an alarm system. My role in the project is designing the product PCB, interfacing all the various sensors and chips that were required to meet project requirements. I worked closely with mechanical and software engineers to ensure that all product requirements were met.
Education
California Polytechnic State University
California Polytechnic State University
Cuesta College
Current Projects
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AI accelerator built on FPGA backend
Design, implementation, and testing of FPGA-based accelerator for AI applications. Created software to automatically compile and implement different accelerator parameters using hls4ml. Automated testing different parameters to discover trade-offs in resource consumption, accuracy, and latency.
- Python
- Tensorflow
- hls4ml
- Vivado HLS
- Vivado
- FPGA
- Zynq-7000
-
Sentiment Analysis of Livestreaming Chat Rooms for Automated Moderation
Training a model to detect inappropriate messages in a chat for a livestream. Creation and training of a transformer-based model to classify messages into categories, and allow for differing punishment based on severity of infraction. Creation of a web interface to allow rule setting, and monitoring of the model.
- Rust
- Tensorflow
- Docker
- Google Cloud Services
-
This Website
Utilizing web technology and automatic deployment to keep this website up to date.
- html
- eleventy.js
Past Projects
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Detection of COVID-19 using Audio Recordings of Coughs using Support Vector Machines
Feature analysis including Mel Frequency Cepstral Coeffecients, Kurtosis, and others. Investigating features for their discriminative capacity. Creation of an SVM model through MATLAB with several parameters to optimize automatically.
- MATLAB
- Machine Learning
-
Implementation of RISC-V Processor on FPGA with 5-stage pipeline and 2-level cache
Implementation and testing of RISC-V architecture on FPGA using technical documentation. Extensive testing of each component to ensure proper functionality. Design and implementation of effecient test benches. Later extension of processor with 5 stage pipeline, and then a 2 level cache. Design, Programming, and testing of small video game to run on the processor with keyboard input and VGA output.
- Verilog
- Vivado
- FPGA
- RISC-V